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? 1. general description the adc1113s125 is a single channel 11-bit analog-to-digital converter (adc) optimized for high dynamic performance and low power at a sample rate of 125 msps. pipelined architecture and output error correction ensure the adc1113s125 is accurate enough to guarantee zero missing codes over the entire operating range. supplied from a 3 v source for analog and a 1.8 v source for the output driver, it outputs data in serial mode via a single differential lane, which complies with the jesd204a standard. the integration of serial peripheral interface (spi) allows the user to easily configure the adcs and the serial output modes. the device also inclu des a programmable full-scale spi to allow a flexible input voltage range from 1 v (p-p) to 2 v (p-p). excellent dynamic performance is maintained from the baseband to input frequencies of 170 mhz or more, making the adc1113s125 ideal for use in communications, imaging, and medical applications. 2. features and benefits 3. applications adc1113s125 single 11-bit adc; serial jesd204a interface rev. 02 ? 2 july 2012 product data sheet ? snr, 66.2 dbfs; sfdr, 87 dbc ? input bandwidth, 600 mhz ? sample rate: 125 msps ? power dissipation, 550 mw at 80 msps ? single channel, 11-bit pipelined adc core ? spi register programming ? 3 v, 1.8 v power supplies ? duty cycle stabilizer ? flexible input voltage range: 1v(p-p)to2v(p-p) ? high intermediate frequency (if) capability ? serial output ? offset binary, two?s complement, gray code ? compliant with jesd204a serial transmission standard ? power-down mode and sleep mode ? pin compatible with adc1613s series, adc1413s series, and adc1213s series ? hvqfn32 package ? wireless and wired broadband communications ? portable instrumentation ? spectral analysis ? imaging systems ? ultrasound equipment
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 2 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 4. ordering information table 1. ordering information type number sampling frequency (msps) package name description version ADC1113S125HN-C1 125 hvqfn32r plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; resin based; body 7 ? 7 ? 0.8 mm sot1152-1
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 3 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 5. block diagram fig 1. block diagram error correction and digital processing clock input stage and duty cycle control adc core 11-bit pipelined t/h input stage system reference and power management adc1113s125 dll pll frame assembly serializer a spi output buffer a scrambler a encoder 8-bit/10-bit a inp inm clkp clkm 8-bit 8-bit 10-bit syncp sclk sdio cs syncn cmln cmlp otr d10 to d0 001aam773 sense dgnd vdda vddd agnd otr
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 4 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 6. pinning information 6.1 pinning 6.2 pin description fig 2. pinning diagram 001aam775 adc1113s125 transparent top view 24 23 22 21 20 19 18 17 terminal 1 index area n.c. cmlp cmln vddd dgnd dgnd vddd dgnd 1 2 3 4 5 6 7 8 clkp vcm reft refb agnd inp inm clkm 9 10 11 12 13 14 15 16 vdda otr cs sdio sclk dgnd vddd vdda 32 31 30 29 28 27 26 25 vref vddd dgnd vdda agnd syncp syncn sense table 2. pin description symbol pin type [1] description clkp 1 i clock input clkm 2 i complementary clock input agnd 3 g analog ground refb 4 o adc bottom reference reft 5 o adc top reference vcm 6 o adc output common voltage inm 7 i adc complementary analog input inp 8 i adc analog input vdda 9 p analog power supply 3 v vdda 10 p analog power supply 3 v sclk 11 i spi clock sdio 12 i/o spi data input/output
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 5 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface [1] p: power supply; g: ground; i: input; o: output; i/o: input/output. 7. limiting values 8. thermal characteristics [1] value for six layers board in still ai r with a minimum of 25 thermal vias. cs 13 i chip select otr 14 o out-of-range information vddd 15 p digital power supply 1.8 v dgnd 16 g digital ground dgnd 17 g digital ground vddd 18 p digital power supply 1.8 v cmlp 19 o serial output cmln 20 o serial complementary output vddd 21 p digital power supply 1.8 v dgnd 22 g digital ground dgnd 23 g digital ground n.c. 24 - not connected syncp 25 i positive synchronization signal from the receiver syncn 26 i negative synchronization signal from the receiver vddd 27 p digital power supply 1.8 v dgnd 28 g digital ground vdda 29 p analog power supply 3 v agnd 30 g analog ground sense 31 i reference programming pin vref 32 i/o voltage reference input/output table 2. pin description ?continued symbol pin type [1] description table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dda analog supply voltage ? 0.4 +4.6 v v ddd(1v8) digital supply voltage (1.8 v) ? 0.4 +2.5 v t stg storage temperature ? 55 +125 ? c t amb ambient temperature ? 40 +85 ? c t j junction temperature - 125 ? c table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient [1] 25.6 k/w r th(j-c) thermal resistance from junction to case [1] 8.6 k/w
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 6 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 9. static characteristics table 5. static characteristics [1] symbol parameter conditions min typ max unit supplies v dda analog supply voltage 2.85 3.0 3.4 v v ddd(1v8) digital supply voltage (1.8 v) 1.65 1.8 1.95 v i dda analog supply current f clk = 125 msps; f i =70mhz -185- ma i ddd(1v8) digital supply current (1.8 v) f clk = 125 msps; f i =70mhz -75- ma p tot total power dissipation f clk = 125 msps - 690 - mw f clk = 105 msps - 625 - mw f clk =80msps - 550 - mw f clk =65msps - 495 - mw p power dissipation power-down mode - 30 - mw standby mode - 150 - mw clock inputs: pins clkp and clkm (ac-coupled) low-voltage positive em itter-coupled logic (lvpecl) v i(clk)dif differential clock input voltage peak-to-peak - 1.6 - v sine v i(clk)dif differential clock input voltage peak ? 0.8 ? 3.0 - v low voltage complementary metal oxide semiconductor (lvcmos) v il low-level input voltage - - 0.3v dda v v ih high-level input voltage 0.7v dda -- v spi: pins cs , sdio, sclk v il low-level input voltage 0 - 0.3v dda v v ih high-level input voltage 0.7v dda -v dda v i il low-level input current ? 10 - +10 ? a i ih high-level input current ? 50 - +50 ? a c i input capacitance - 4 - pf analog inputs: pins inp and inm i i input current track mode ? 5- +5 ? a r i input resistance track mode - 15 - ? c i input capacitance track mode - 5 - pf v i(cm) common-mode input voltage track mode 1.1 1.5 2 v b i input bandwidth - 600 - mhz v i(dif) differential input voltage peak-to-peak 1 - 2 v
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 7 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface voltage controlled regulator output: pin vcm v o(cm) common-mode output voltage -0.5v dda -v i o(cm) common-mode output current -4 - ma reference voltage in put/output: pin vref v vref voltage on pin vref output 0.5 - 1 v input 0.5 - 1 v data outputs: pins cmlp, cmln output levels, v ddd(1v8) = 1.8 v; swing_sel[2:0] = 000 v ol low-level output voltage dc-coupled; output - 1.5 - v ac-coupled - 1.35 - v v oh high-level output voltage dc-coupled; output - 1.8 - v ac-coupled - 1.65 - v output levels, v ddd(1v8) = 1.8 v; swing_sel[2:0] = 001 v ol low-level output voltage dc-coupled; output - 1.45 - v ac-coupled - 1.275 - v v oh high-level output voltage dc-coupled; output - 1.8 - v ac-coupled - 1.625 - v output levels, v ddd(1v8) = 1.8 v; swing_sel[2:0] = 010 v ol low-level output voltage dc-coupled; output - 1.4 - v ac-coupled - 1.2 - v v oh high-level output voltage dc-coupled; output - 1.8 - v ac-coupled - 1.6 - v output levels, v ddd(1v8) = 1.8 v; swing_sel[2:0] = 011 v ol low-level output voltage dc-coupled; output - 1.35 - v ac-coupled - 1.125 - v v oh high-level output voltage dc-coupled; output - 1.8 - v ac-coupled - 1.575 - v output levels, v ddd(1v8) = 1.8 v; swing_sel[2:0] = 100 v ol low-level output voltage dc-coupled; output - 1.3 - v ac-coupled - 1.05 - v v oh high-level output voltage dc-coupled; output - 1.8 - v ac-coupled - 1.55 - v serial configuration: pins syncp, syncn v il low-level input voltage differential; input - 0.95 - v v ih high-level input voltage differential; input - 1.47 - v accuracy inl integral non-linearity ? 5- +5 lsb dnl differential non-linear ity guaranteed no missing codes ? 0.95 ? 0.5 +0.95 lsb e offset offset error - ? 2- mv table 5. static characteristics [1] ?continued symbol parameter conditions min typ max unit
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 8 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface [1] typical values measured at v dda =3v, v ddd(1v8) =1.8v, t amb =25 ? c. minimum and maximum values are across the full temperature range t amb = ? 40 ? c to +85 ? c at v dda =3v, v ddd(1v8) = 1.8 v; v i(inp) ? v i(inm) = ? 1 dbfs; internal reference mode; 100 ? differential applied to serial outputs; unless otherwise specified. 10. dynamic characteristics 10.1 dynamic characteristics e g gain error full-scale - ? 0.5 - % supply psrr power supply rejection ratio 200 mv (p-p) on pin vdda; f i =dc - ? 54 - db table 5. static characteristics [1] ?continued symbol parameter conditions min typ max unit table 6. dynamic characteristics [1] symbol parameter conditions min typ max unit ? 2h second harmonic level f i =3mhz - 88 - dbc f i =30mhz - 87 - dbc f i =70mhz - 85 - dbc f i =170mhz - 83 - dbc ? 3h third harmonic level f i =3mhz - 87 - dbc f i =30mhz - 86 - dbc f i =70mhz - 84 - dbc f i =170mhz - 82 - dbc thd total harmonic distortion f i =3mhz - 84 - dbc f i =30mhz - 83 - dbc f i =70mhz - 81 - dbc f i =170mhz - 79 - dbc enob effective number of bits f i =3mhz - 10.7 - bits f i = 30 mhz - 10.7 - bits f i = 70 mhz - 10.7 - bits f i =170mhz - 10.6 - bits snr signal-to-noise ratio f i =3mhz - 66.2 - dbfs f i = 30 mhz - 66.2 - dbfs f i = 70 mhz - 66.0 - dbfs f i =170mhz - 65.8 - dbfs sfdr spurious-free dynamic range f i =3mhz - 87 - dbc f i =30mhz - 86 - dbc f i =70mhz - 84 - dbc f i =170mhz - 82 - dbc
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 9 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface [1] typical values measured at v dda =3v, v ddd(1v8) =1.8v, t amb =25 ? c. minimum and maximum values are across the full temperature range t amb = ? 40 ? c to +85 ? c at v dda =3v, v ddd(1v8) = 1.8 v; v i(inp) ? v i(inm) = ? 1 dbfs; internal reference mode; 100 ? differential applied to serial outputs; unless otherwise specified. 10.2 clock and digital output timing [1] typical values measured at v dda =3v, v ddd(1v8) =1.8v, t amb =25 ? c. minimum and maximum values are across the full temperature range t amb = ? 40 ? c to +85 ? c at v dda =3v, v ddd(1v8) = 1.8 v; v i(inp) ? v i(inm) = ? 1 dbfs; internal reference mode; 100 ? differential applied to serial outputs; unless otherwise specified. imd intermodulation distortion f i =3mhz - 89 - dbc f i =30mhz - 88 - dbc f i =70mhz - 86 - dbc f i =170mhz - 84 - dbc ? ct(ch) channel crosstalk f i =70mhz - 100 - dbc table 6. dynamic characteristics [1] ?continued symbol parameter conditions min typ max unit table 7. clock and digital output characteristics [1] symbol parameter conditions min typ max unit pins clkp and clkm f clk clock frequency 100 - 125 msps t lat(data) data latency time clock cycles 160 - 170 ns ? clk clock duty cycle dcs_en = logic 1 30 50 70 % t d(s) sampling delay time - 0.8 - ns t wake wake-up time - 76 - ? s
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 10 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 10.3 serial output timing the eye diagram of the serial output is show n in figure 3 and figure 4. test conditions are: ? 3.125 gbps data rate ? t amb =25c ? dc-coupling with two different re ceiver common-mode voltages fig 3. eye diagram at 1 v receiver common-mode fig 4. eye diagram at 2 v receiver common-mode 005aaa088 005aaa089
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 11 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 10.4 spi timing [1] typical values measured at v dda =3v, v ddd(1v8) = 1.8 v, t amb =25 ? c. minimum and maximum values are across the full temperature range t amb = ? 40 ? c to +85 ? c at v dda =3v, v ddd(1v8) =1.8v; v i(inp) ? v i(inm) = ? 1 dbfs; internal reference mode; 100 ? differential applied to serial outputs; unless otherwise specified. table 8. spi timing characteristics [1] symbol parameter conditions min typ max unit t w(sclk) sclk pulse width - 40 - ns t w(sclkh) sclk high pulse width -16- ns t w(sclkl) sclk low pulse width -16- ns t su set-up time data to sclk high -5- ns cs to sclk high -5- ns t h hold time data to sclk high -2- ns cs to sclk high22 -2- ns f clk(max) maximum clock frequency -25- mhz fig 5. spi timing t su sdio sclk r/w w1 w0 a12 a11 d2 d1 d0 t su t h t h t w(sclk) 005aaa065 cs t w(sclkl) t w(sclkh)
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 12 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 11. application information 11.1 analog inputs 11.1.1 input stage description the analog input of the adc1113s supports a differential or a single-ended input drive. optimal performance is achieved using diff erential inputs with the common-mode input voltage (v i(cm) ) on pins inp and inm set to 0.5v dda . the full-scale analog input voltage range is configurable between 1 v (p-p) and 2 v (p-p) via a programmable internal reference (see section 11.2 and table 21). figure 6 shows the equivalent circuit of th e sample-and-hold input stage, including electrostatic discharge (esd) protection and circuit and package parasitics. the sample phase occurs when the internal clock (derived from the clock signal on pin clkp/clkm) is high. the voltage is then he ld on the sampling capacitors. when the clock signal goes low, the stage enters the hold phase and the voltage information is transmitted to the adc core. 11.1.2 anti-kickback circuitry anti-kickback circuitry (rc filter in figure 7 ) is needed to counteract the effects of a charge injection generated by the sampling capacitance. the rc filter is also used to filter noise from the signal before it reaches the sampling stage. the value of the capacitor should be ch osen to maximize noise attenuation without degrading the settling time excessively. fig 6. input sampling circuit 005aaa185 inp package esd parasitics switch r on = 15 c s c s switch r on = 15 inm 8 7 internal clock internal clock
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 13 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface the component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. 11.1.3 transformer the configuration of the transf ormer circuit is determined by the input frequency. the configuration shown in figure 8 would be suitable for a baseband application. fig 7. anti-kickback circuit table 9. rc-coupling versus input frequency, typical values input frequency (mhz) resistance ( ? ) capacitance (pf) 32512 70 12 8 170 12 8 005aaa073 r r c inp inm fig 8. single transformer configuration 005aaa044 100 nf 100 nf 100 nf 100 nf 25 25 25 25 12 pf inp inm vcm 100 nf analog input adt1-1wt 100 nf
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 14 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface the configuration shown in figure 9 is reco mmended for high frequency applications. in both cases, the choice of transformer is a compromise between cost and performance. 11.2 system reference and power management 11.2.1 internal/external reference the adc1113s has a stable and accurate built-in internal reference voltage to adjust the adc full-scale. this reference voltage can be se t internally via spi or with pins vref and sense (see figure 11 to figure 14), in 1 db steps between 0 db and ? 6 db, via spi control bits intref[2:0] (when bit intref_en = logic 1; see table 21). the equivalent reference circuit is shown in figure 10. an external reference is also possible by providing a voltage on pin vref as described in figure 14. fig 9. dual transformer configuration 005aaa045 100 nf 100 nf 100 nf 100 nf 12 12 8.2 pf inp inm vcm 50 50 50 50 adt1-1wt adt1-1wt analog input
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 15 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface if bit intref_en is set to logic 0, the reference voltage is determined either internally or externally as detailed in table 10. figure 11 to figure 14 illustrate how to conn ect the sense and vref pins to select the required reference voltage source. fig 10. reference equivalent schematic table 10. reference modes mode spi bit, ?internal reference? sense pin vref pin full-scale (v (p-p)) internal (figure 11) 0 gnd 330 pf capacitor to gnd 2 internal (figure 12) 0 vref pin = sense pin and 330 pf capacitor to gnd 1 internal, spi mode (figure 12) 1 vref pin = sense pin and 330 pf capacitor to gnd 1 to 2 external (figure 14) 0 v dda external voltage from 0.5 v to 1 v 1 to 2 ext_ref ext_ref 005aaa164 reft refb sense vref selection logic bandgap reference adc core buffer reference amp
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 16 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 11.2.2 programmable full-scale the full-scale is programmable between 1 v (p-p) to 2 v (p-p) (see table 11). 11.2.3 common-mode output voltage (v o(cm) ) an 0.1 ? f filter capacitor should be connected between pin vcm and ground to ensure a low-noise common-mode output voltage. when ac-coupled, this pin can be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point. fig 11. internal reference, 2 v (p-p) full-scale fig 12. internal reference, 1 v (p-p) full-scale fig 13. internal reference vi a spi, 1 v (p-p) to 2 v (p-p) full-scale fig 14. external reference, 1 v (p-p) to 2 v (p-p) full-scale 330 pf vref sense 005aaa116 reference equivalent schematic 330 pf 005aaa117 vref sense reference equivalent schematic reference equivalent schematic 330 pf 005aaa118 vref sense 0.1 f vdda v 005aaa119 vref sense reference equivalent schematic table 11. reference spi gain control intref[2:0] level (db) full-scale (v (p-p)) 000 0 2 001 ? 11.78 010 ? 21.59 011 ? 31.42 100 ? 41.26 101 ? 51.12 110 ? 61 111 not used x
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 17 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 11.2.4 biasing the common-mode input voltage (v i(cm) ) on pins inp and inm should be set externally to 0.5v dda for optimal performance and should always be between 0.9 v and 2 v. 11.3 clock input 11.3.1 drive modes the adc11113s125 can be driven differentially (lvpecl). it can also be driven by a single-ended lvcmos signal connected to pin clkp (clkm should be connected to ground via a capacitor). fig 15. reference equivalent schematic 1.5 v vcm 0.1 f package esd parasitics 005aaa051 common-mode reference adc core a. rising edge lvcmos b. falling edge lvcmos fig 16. lvcmos single-ended clock input lvcmos clock input clkp clkm 005aaa174 005aaa053 lvcmos clock input clkp clkm
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 18 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 11.3.2 equivalent input circuit the equivalent circuit of the input clock buf fer is shown in figure 18. the common-mode voltage of the differential input stage is set via internal 5 k ? resistors. a. sine clock input b. sine clock input (with transformer) c. lvpecl clock input fig 17. differential clock input sine clock input clkp clkm 005aaa173 sine clock input clkp clkm 005aaa054 lvpecl clock input 005aaa172 clkp clkm v cm(clk) = common-mode voltage of the differential input stage. fig 18. equivalent input circuit clkp clkm 005aaa081 5 k 5 k v cm(clk) se_sel se_sel package esd parasitics
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 19 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface single-ended or differential clock inputs can be selected via the spi (see table 20). if single-ended is selected, the input pin (clkm or clkp) is selected via control bit se_sel. if single-ended is implemented without settin g bit se_sel accordingly, the unused pin should be connected to ground via a capacitor. 11.3.3 duty cycle stabilizer the duty cycle stabilizer can improve th e overall performance of the adc by compensating the input clock signal duty cycle . when the duty cycle stabilizer is active (bit dcs_en = logic 1; see table 20), the circuit can handle signals with duty cycles of between 30 % and 70 % (typical). when t he duty cycle stabilizer is disabled (dcs_en = logic 0), the input clock signal s hould have a duty cycle of between 45 % and 55 %. 11.3.4 clock input divider the adc1113s contains an input clock divider t hat divides the incoming clock by a factor of 2 (when bit clkdiv2_sel = logic 1; see table 20). this feature allows the user to deliver a higher clock frequency with better jitter performance, leading to a better snr result once acquisition has been performed. 11.4 digital outputs 11.4.1 serial output equivalent circuit the jesd204a standard specifies that if the receiver and the transmitter are dc-coupled, both must be fed fr om the same supply. the output should be terminated when 100 ? (typical) is reached at the receiver side. table 12. duty cycle stabilizer bit dcs_en description 0 duty cycle stabilizer disable 1 duty cycle stabilizer enable fig 19. cml output connection to the receiver (dc-coupled) v ddd v ddd cmlp cmln agnd 005aaa197 12 ma to 26 ma 100 + receiver 50 50 -
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 20 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 11.5 jesd204a serializer for more information about the jesd204a standard refer to the jedec web site. 11.5.1 digital jesd204a formatter the block placed after the adc core is used to implement all functions of the jesd204a standard. this ensures signal integrity and gua rantees the clock and t he data recovery at the receiver side. the block is highly parameterized and can be configured in various ways depending on the sampling frequency and the number of lanes used. fig 20. cml output connection to the receiver (ac-coupled) cmlp cmln 12 ma to 26 ma 100 50 50 10 nf 10 nf 005aaa187 v ddd - + receiver fig 21. general overview of the esd204a serialier frame to octets f octets scrambler tx transport layer cf: position of controls bits hd: frame boundary break padding with tails bits (tt) m (n' s) bits l (f) octets l octets n' = n + cs s samples per frame cycle n bits from cr 0 + cs bits for control m converters l lanes tx controller lane 0 8-bit/ 10-bit ser alignment character generator sync~ 005aaa198
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 21 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 11.5.2 adc core output codes versus input voltage table 13 shows the data output codes for a given analog input voltage. fig 22. detailed view of the jesd204a serializer with debug functionality n and cs 00 scr prbs 8-bit/ 10-bit 01 00 01 10 11 '0' '0/1' prbs 8 n + cs 11 + 1 11 + 1 11 + 1 adc pll and dll frame clk character clk bit clk 10 ser 11 10 00 1 f 10f dummy adc_pd prbs frame assembly 001aam774 sync_request adc_mode[1:0] scr_in_mode lane_mode[1:0] swing_sel[2:0] lane_pol fsm (frame assembly character replication ila test mode) table 13. output codes versus input voltage inp ? inm (v) offset binary two?s complement otr < ? 1 000 0000 0000 100 0000 0000 1 ? 1.0000000 000 0000 0000 100 0000 0000 0 ? 0.9990234 000 0000 0001 100 0000 0001 0 ? 0.9980469 000 0000 0010 100 0000 0010 0 ? 0.9970703 000 0000 0011 100 0000 0011 0 ? 0.996093 000 0000 0100 100 0000 0100 0 .... .... .... 0 ? 0.0019531 011 1111 1110 111 1111 1110 0 ? 0.0009766 011 1111 1111 111 1111 1111 0 0.0000000 100 0000 0000 000 0000 0000 0 +0.0009766 100 0000 0001 000 0000 0001 0 +0.0019531 100 0000 0010 000 0000 0010 0 .... .... .... 0 +0.9970703 111 1111 1011 011 1111 1011 0 +0.99990845 111 1111 1100 011 1111 1100 0 +0.9980469 111 1111 1101 011 1111 1101 0 +0.9990234 111 1111 1110 011 1111 1110 0 +1.0000000 111 1111 1111 011 1111 1111 0 > +1 111 1111 1111 011 1111 1111 1
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 22 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 11.6 serial peripheral interface (spi) 11.6.1 register description the adc1113s serial interface is a synchron ous serial communicati ons port allowing for easy interfacing with many industry microprocessors. it provides access to the registers that control the operation of the chip in both read and write modes. this interface is configured as a 3- wire type (sdio as bidirectional pin). pin sclk acts as the serial clock and pin cs acts as the serial chip select. each read/write operation is sequenced by the cs signal and enabled by a low level to to drive the chip with n bytes, depending on the content of the instruction byte (see table 14). [1] r/w indicates whether a read (logic 1) or write (l ogic 0) transfer occurs after the instruction byte. [1] bits w1 and w0 indicate the number of bytes transferred. bits a12 to a0 indicate the address of the register being accessed. in the case of a multiple byte transfer, this address is the first register to be accessed. an address counter is incremented to access subsequent addresses. the steps involved in a data transfer are as follows: 1. the falling edge on pin cs in combination with a rising edge on pin sclk determine the start of communications. 2. the first phase is the transfer of the 2-byte instruction. 3. the second phase is the transfer of the data which can vary in length but is always a multiple of 8 bits. the most significant bit (msb) is always sent first (for instruction and data bytes) 4. a rising edge on pin cs indicates the end of data transmission. table 14. spi instruction bytes msb lsb bit 76543210 description r/w [1] w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 table 15. read or write mode access description r/w [1] description 0 write mode operation 1 read mode operation table 16. number of bytes to be transferred w1 w0 number of bytes transferred 001 byte 012 bytes 103 bytes 1 1 4 or more bytes
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 23 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface fig 23. transfer diagram for tw o data bytes (3-wire type) cs sclk sdio r/w w1 w0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d3 d2 d1 d0 d0 d7 d6 d5 d4 instruction bytes register n (data) register n + 1 (data) 005aaa086
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 24 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 11.6.2 channel control table 17. register allocation map address (hex) register name access [1] bit definition default [2] (bin) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adc control register 0003 spi control r/w - - - - - - enable - 1111 1111 0005 reset and power-down modes r/w sw_rst - - - - - pd[1:0] 0000 0000 0006 clock r/w - - - se_sel diff_se - clkdiv2_sel dcs_en 0000 000* 0008 vref r/w - - - - intref_en intref[2:0] 0000 0000 0013 offset r/w - - dig_offset[5:0] 0000 0000 0014 test pattern 1 r/w - - - - - testpat_1[2:0] 0000 0000 0015 test pattern 2 r/w testpat_2[10:3] 0000 0000 0016 test pattern 3 r/w testpat_3[2:0] - - - - - 0000 0000 jesd204a control 0801 ser_status r rxsync _error reserved[2:0] 0 0 por_tst reserved 0001 0000 0802 ser_reset r/w sw_rst 0 0 0 fsm_sw_ rst 0 0 0 0000 0000 0805 ser_control1 r/w 0 reserved sync_ pol sync_ single_ ended 1 rev_ scr rev_ encoder rev_ serial 0100 1001 0808 ser_analog_ctrl r/w 0 0 0 0 0 swing_sel[2:0] 0000 0011 0809 ser_scramblera r/w 0 lsb_init[6:0] 0000 0000
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 25 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface [1] an "*" in the r/w column means that this register is subject to control acce ss conditions in write mode. [2] an "*" in the default column replaces a bit w hose value depends on the binary level of external pins. 080a ser_scramblerb r/w msb_init[7:0] 1111 1111 080b ser_prbs_ctrl r/w 0 0 0 0 0 0 prbs_type[1:0] 0000 0000 0820 cfg_0_did r did[7:0] 1110 1101 0821 cfg_1_bid r/w* 0 0 0 0 bid[3:0] 0000 1010 0822 cfg_3_scr_l r/w* scr 0 0 0 0 0 0 l 0000 0000 0823 cfg_4_f r/w* 0 0 0 0 0 f[2:0] 0000 0*** 0824 cfg_5_k r/w* 0 0 0 k[4:0] 000* **** 0825 cfg_6_m r/w* 0 0 0 0 0 0 0 m 0000 000* 0826 cfg_7_cs_n r/w* 0 cs[0] 0 0 n[3:0] 0100 0001 0827 cfg_8_np r/w 0 0 0 np[4:0] 0000 1111 0828 cfg_9_s r/w* 0 0 0 0 0 0 0 s 0000 0000 0829 cfg_10_hd_cf r/w* hd 0 0 0 0 0 cf[1:0] *000 0000 082d cfg_02_2_lid r/w* 0 0 0 lid[4:0] 0001 1100 084d cfg02_13_fchk r fchk[7:0] **** **** 0871 lane_0_ctrl r/w 0 scr_in_ mode lane_mode[1:0] 0 lane_ pol reserved lane_pd 0000 0000 0891 adc_0_ctrl r/w 0 0 adc_mode[1:0] 0 0 0 adc_pd 0000 0000 table 17. register allocation map ?continued address (hex) register name access [1] bit definition default [2] (bin) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 26 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 11.6.3 register description 11.6.3.1 adc control registers table 18. register spi control (address 0003h) default values are highlighted. bit symbol access value description 7 to 2 - - 111111 not used 1 enable r/w adc spi control enable: 0 adc does not get the next spi command 1 adc gets the next spi command 0 - - 1 not used table 19. register reset and power-down mode (address 0005h) default values are highlighted. bit symbol access value description 7 sw_rst r/w reset digital part: 0 no reset 1 performs a reset of the digital part 6 to 2 - - 00000 not used 1 to 0 pd[1:0] r/w power-down mode: 00 normal (power-up) 01 full power-down 10 sleep 11 normal (power-up) table 20. register clock (address 0006h) default values are highlighted. bit symbol access value description 7 to 5 - - 000 not used 4 se_sel r/w select se clock input pin: 0 select clkm input 1 select clkp input 3 diff_se r/w differential/single-ended clock input select: 0 fully differential 1 single-ended 2 - - 0 not used 1 clkdiv2_sel r/w select clock input divider by 2: 0 disable 1 enable 0 dcs_en r/w duty cycle stabilizer enable: 0 disable 1 enable
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 27 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface table 21. register vref (address 0008h) default values are highlighted. bit symbol access value description 7 to 4 - - 0000 not used 3 intref_en r/w enable internal programmable vref mode: 0 disable 1 enable 2 to 0 intref[2:0] r/w programmable internal reference: 000 0 db (fs = 2 v) 001 ? 1 db (fs = 1.78 v) 010 ? 2 db (fs = 1.59 v) 011 ? 3 db (fs = 1.42 v) 100 ? 4 db (fs = 1.26 v) 101 ? 5 db (fs = 1.12 v) 110 ? 6 db (fs = 1 v) 111 not used table 22. digital offset adjustment (address 0013h) default values are highlighted. register offset decimal dig_offset[5:0] +31 011111 +31 lsb ... ... ... 0 000000 0 ... ... ... ? 32 100000 ? 32 lsb table 23. register test pattern 1 (address 0014h) default values are highlighted. bit symbol access value description 7 to 3 - - 00000 not used 2 to 0 testpat_1[2:0] r/w digital test pattern: 000 off 001 mid-scale 010 ? fs 011 + fs 100 toggle ?1111..1111?/?0000..0000? 101 custom test pattern, to be written in register 0015h and 0016h 110 ?010101...? 111 ?101010...?
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 28 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 11.6.4 jesd204a digital control registers table 24. register test pattern 2 (address 0015h) default values are highlighted. bit symbol access value description 7 to 0 testpat_2[10:3] r/w 00000000 custom digital test pattern (bit 10 to 3) table 25. register test pattern 3 (address 0016h) default values are highlighted. bit symbol access value description 7 to 5 testpat_3[2:0] r/w 000 custom digital test pattern (bit 2 to 0) 4 to 0 - - 00000 not used table 26. ser_status (address 0801h) default values are highlighted. bit symbol access value description 7 rxsync_error r 0 set to 1 when a synchronization error occurs 6 to 4 reserved[2:0] - 001 reserved 3 to 2 - - 00 not used 1por_tst r 0 power-on-reset 0 reserved - 0 reserved table 27. ser_reset (address 0802h) default values are highlighted. bit symbol access value description 7sw_rst r/w 0 initiates a software reset of the jesd204a unit 6 to 4 - - 000 not used 3fsm_sw_rst r/w 0 initiates a software reset of the internal state machine of jesd204a unit 2 to 0 - - 000 not used table 28. ser_control1 (address 0805h) default values are highlighted. bit symbol access value description 7 - - 0 not used 6 reserved - 1 reserved 5 sync_pol r/w defines the synchronization signal polarity: 0 synchronization signal is active low 1 synchronization signal is active high 4 sync_single_ended r/w defines the input mode of the synchronization signal: 0 synchronization input mode is set in differential mode 1 synchronization input mode is set in single-ended mode 3 - - 1 not used 2 rev_scr - lsbs are swapped with msbs at the scrambler input: 0 disable 1 enable
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 29 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 1 rev_encoder - lsbs are swapped with m sbs at the 8-bit/10-bit encoder input: 0 disable 1 enable 0 rev_serial - lsbs are swapped with msbs at the lane input: 0 disable 1enable table 28. ser_control1 (address 0805h) ?continued default values are highlighted. bit symbol access value description table 29. ser_analog_ctrl (address 0808h) default values are highlighted. bit symbol access value description 7 to 3 - - 00000 not used 2 to 0 swing_sel[2:0] r/w 011 defines the swing output for the lane pads table 30. ser_scramblera (address 0809h) default values are highlighted. bit symbol access value description 7 - - 0 not used 6 to 0 lsb_init[6:0] r/w 0000000 defines the initialization vector for the scrambler polynomial (lower) table 31. ser_scramblerb (address 080ah) default values are highlighted. bit symbol access value description 7 to 0 msb_init[7:0] r/w 11111111 defines the initialization vector for the scrambler polynomial (upper) table 32. ser_prbs_ctrl (address 080bh) default values are highlighted. bit symbol access value description 7 to 2 - - 000000 not used 1 to 0 prbs_type[1:0] r/w defines the type of pseudo-random binary sequence (prbs) generator to be used: 00 (reset) prbs-7 01 prbs-7 10 prbs-23 11 prbs-31 table 33. cfg_0_did (address 0820h) default values are highlighted. bit symbol access value description 7 to 0 did[7:0] r 11101101 defines the device (= link) identification number
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 30 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface table 34. cfg_1_bid (address 0821h) default values are highlighted. bit symbol access value description 7 to 4 - - 0000 not used 3 to 0 bid[3:0] r/w 1010 defines the bank id ? extension to did table 35. cfg_3_scr_l (address 0822h) default values are highlighted. bit symbol access value description 7 scr r/w 0 scrambling enabled 6 to 1 - - 000000 not used 0 l r/w 0 defines the number of lanes per converter device, minus 1 table 36. cfg_4_f (address 0823h) default values are highlighted. bit symbol access value description 7 to 3 - - 00000 not used 2 to 0 f[2:0] r/w *** defines the number of octets per frame, minus 1 table 37. cfg_5_k (address 0824h) default values are highlighted. bit symbol access value description 7 to 5 - - 000 not used 4 to 0 k[4:0] r/w ***** defines the number of frames per multiframe, minus 1 table 38. cfg_6_m (address 0825h) default values are highlighted. bit symbol access value description 7 to 1 - - 0000000 not used 0m r/w * defines the number of converters per device, minus 1 table 39. cfg_7_cs_n (address 0826h) default values are highlighted. bit symbol access value description 7 - - 0 not used 6 cs[0] r/w 1 defines the number of control bits per sample, minus 1 5 to 4 - - 00 not used 3 to 0 n[3:0] r/w 0001 defines the converter resolution table 40. cfg_8_np (address 0827h) default values are highlighted. bit symbol access value description 7 to 5 - - 000 not used 4 to 0 np[4:0] r/w 01111 defines the total number of bits per sample, minus 1
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 31 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface table 41. cfg_9_s (address 0828h) default values are highlighted. bit symbol access value description 7 to 1 - - 0000000 not used 0s r/w 0 defines number of samples per converter per frame cycle table 42. cfg_10_hd_cf (address 0829h) default values are highlighted. bit symbol access value description 7 hd r/w * defines high density format 6 to 2 - - 00000 not used 1 to 0 cf[1:0] r/w 00 defines number of cont rol words per frame clock cycle per link. table 43. cfg_02_2_lid (address 082dh) default values are highlighted. bit symbol access value description 7 to 5 - - 000 not used 4 to 0 lid[4:0] r/w 11100 defines lane identification number table 44. cfg02_13_fchk (address 084dh) default values are highlighted. bit symbol access value description 7 to 0 fchk[7:0] r ******** defines the checksum value for lane checksum corresponds to the sum of all the link configuration parameters module 256 (as defined in jedec standard no.204a) table 45. lane_0_ctrl (address 0871h) default values are highlighted. bit symbol access value description 7 - - 0 not used 6 scr_in_mode r/w defines the input type fo r scrambler and 8-bit/10-bit units 0 (reset) (normal mode) = input of the scrambler and 8-bit/10-bit units is the output of the frame assembly unit. 1 input of the scrambler and 8-bit/10-bit units is the prbs generator (prbs type is defined with ?prbs_type[1:0]? (ser_prbs_ctrl register) 5 to 4 lane_mode[1:0] r/w defines output type of lane output unit: 00 (reset) normal mode: lane output is the 8-bit/10-bit output unit 01 constant mode: lane output is set to a constant (0 ? 0) 10 toggle mode: lane output is toggling between 0 ? 0 and 0 ? 1 11 prbs mode: lane output is th e prbs generator (prbs type is defined with ?prbs_type[1:0] ? (ser_prbs_ctrl register) 3 - - 0 not used
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 32 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 2 lane_pol r/w defines lane polarity: 0 lane polarity is normal 1 lane polarity is inverted 1 reserved r/w 0 reserved 0 lane_pd r/w lane power-down control: 0 lane is operational 1 lane is in power-down mode table 45. lane_0_ctrl (address 0871h) ?continued default values are highlighted. bit symbol access value description table 46. adc_0_ctrl (address 0891h) default values are highlighted. bit symbol access value description 7 to 6 - - 00 not used 5 to 4 adc_mode[1:0] r/w defines input type of jesd204a unit 00 (reset) adc output is connected to the jesd204a input 01 not used 10 jesd204a input is fed with a dummy constant, set to: otr = 0 and adc[13:0] = ?10011011101010? 11 jesd204a is fed with a prbs generator (prbs type is defined with ?prbs_type[1:0]? (s er_prbs_ctrl register) 3 to 1 - - 000 not used 0 adc_pd r/w adc power-down control: 0 adc is operational 1 adc is in power-down mode
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 33 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 12. package outline fig 24. package outline sot1152-1 (hvqfn32) references outline version european projection issue date iec jedec jeita sot1152-1 - - - - - - - - - sot1152-1_po 09-10-13 09-11-16 unit mm max nom min 0.90 0.80 0.75 0.28 0.23 0.18 4.05 4.00 3.95 7.1 7.0 6.9 4.05 4.00 3.95 4.55 4.55 0.55 0.50 0.45 0.08 0.1 a dimensions hvqfn32r: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; resin based; body 7 x 7 x 0.8 mm sot1152-1 bd 7.1 7.0 6.9 d h ee h e 0.65 e 1 e 2 ll 1 0.10 0.05 0.00 v 0.1 w 0.05 yy 1 0 2.5 5 mm scale b a d e x c y c y 1 terminal 1 index area d h e h l 1 l 17 a detail x terminal 1 index area b e 2 e 1 e e 1/2 e 1/2 e a c b ? v c ? w 16 9 25 32 24 8 1 note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 34 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 13. abbreviations table 47. abbreviations acronym description adc analog-to-digital converter dcs duty cycle stabilizer esd electrostatic discharge if intermediate frequency imd intermodulation distortion lsb least significant bit lvcmos low-voltage complementary metal-oxide semiconductor lvpecl low-voltage positive emitter-coupled logic msb most significant bit otr out-of-range prbs pseudo-random binary sequence sfdr spurious-free dynamic range snr signal-to-noise ratio spi serial peripheral interface tx transmitter
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 35 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 14. revision history 15. contact information for more information or sales office addresses, please visit: http://www.idt.com table 48. revision history document id release date data sheet status change notice supersedes adc1113s125 v.2 20120702 product data sheet - adc1113s125 v.1 adc1113s125 v.1 20110315 product data sheet - -
adc1113s125 2 ? idt 2012. all rights reserved. product data sheet rev. 02 ? 2 july 2012 36 of 36 integrated device technology adc1113s125 single 11-bit adc; serial jesd204a interface 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 thermal characteristics . . . . . . . . . . . . . . . . . . 5 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 8 10.1 dynamic characteristics . . . . . . . . . . . . . . . . . . 8 10.2 clock and digital output timing . . . . . . . . . . . . . 9 10.3 serial output timing . . . . . . . . . . . . . . . . . . . . . 10 10.4 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 application information. . . . . . . . . . . . . . . . . . 12 11.1 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . 12 11.1.1 input stage description . . . . . . . . . . . . . . . . . . 12 11.1.2 anti-kickback circuitry . . . . . . . . . . . . . . . . . . . 12 11.1.3 transformer . . . . . . . . . . . . . . . . . . . . . . . . . . 13 11.2 system reference and power management . . 14 11.2.1 internal/external reference . . . . . . . . . . . . . . . 14 11.2.2 programmable full-scale . . . . . . . . . . . . . . . . 16 11.2.3 common-mode output voltage (v o(cm) ) . . . . . 16 11.2.4 biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11.3 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11.3.1 drive modes. . . . . . . . . . . . . . . . . . . . . . . . . . 17 11.3.2 equivalent input circuit . . . . . . . . . . . . . . . . . . 18 11.3.3 duty cycle stabilizer . . . . . . . . . . . . . . . . . . . . 19 11.3.4 clock input divider . . . . . . . . . . . . . . . . . . . . . 19 11.4 digital outputs . . . . . . . . . . . . . . . . . . . . . . . . 19 11.4.1 serial output equivalent circuit . . . . . . . . . . . . 19 11.5 jesd204a serializer . . . . . . . . . . . . . . . . . . . 20 11.5.1 digital jesd204a formatter . . . . . . . . . . . . . . 20 11.5.2 adc core output codes versus input voltage . 21 11.6 serial peripheral interface (spi) . . . . . . . . . . 22 11.6.1 register description . . . . . . . . . . . . . . . . . . . . 22 11.6.2 channel control . . . . . . . . . . . . . . . . . . . . . . . 24 11.6.3 register description . . . . . . . . . . . . . . . . . . . . 26 11.6.3.1 adc control registers. . . . . . . . . . . . . . . . . . . 26 11.6.4 jesd204a digital control registers . . . . . . . . 28 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 33 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 34 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 35 15 contact information . . . . . . . . . . . . . . . . . . . . 35 16 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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